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Overview
The Discovery™ Verification Platform is an integrated system, RTL, equivalence checking, and mixed-signal verification solution that provides high performance and efficient interactions among best-in-class technologies. These technologies include mixed-HDL simulation, mixed-signal simulation, system-level verification, assertions, verification IP, code coverage, functional coverage, testbenches, and formal analysis. Discovery’s components support Verilog, VHDL, mixed-HDL, SystemVerilog, SystemC and analog/mixed-signal designs.
- Key Benefits
- Best-in-class tools and verification IP, enabling first pass silicon success
- Advanced design-for-verification methodology to eliminate bugs
- High-performance solutions built on industry leading simulators enabling fast, flexible SoC and system verification
- HSIMplus
- HSPICE
- Innovator
- NanoSim
- Saber
- SpiceExplorer
- System Studio
- WaveView Analyzer
- VCS
- XA Technology
- Ensured accuracy through use of common foundry-certified models
Verification Challenges
The need for more flexibility, functionality and performance across multiple levels of design is driving demand for better tools and technology. Whether designing high performance electro-mechanical flight systems or a multi-processor SoC, designers are facing formidable challenges to deliver high quality product designs on time. Verification of these state-of-the-art systems is becoming a severe bottleneck as designers face the sometimes daunting task of eliminating all the bugs in their design.
The Discovery Verification Platform provides several key solutions for meeting the verification challenges of advanced product design.By providing engineers the latest technology, tools, IP and a proven methodology based on industry standards to completely test the most complex designs, Discovery Verification Platform reduces the burden of verification and improves time-to-market.
System Analysis and Design
The complexity of system level design is compounded by ever increasing functionality and more intricate applications. This leads to greater challenges for the creation and verification of these designs. In a rapidly evolving technology environment, requirements can run the design gamut from analyzing the efficiency of an entire fuel-cell vehicle to improving a picture-acquisition algorithm for an advanced digital camera. Advanced system-level modeling and simulation technologies must encompass electro-mechanical, analog, and digital analysis of hardware and software design and verification to provide not only a fully-integrated solution, but also the right solution for the right product at the right time.
Smart RTL Verification
Today, RTL verification is the biggest challenge and the most time-consuming part of the product development cycle. To achieve first-pass silicon all the RTL code must be thoroughly and effectively verified. This requires advanced test generation, simulation, formal analysis Verification IP, and comprehensive coverage technologies.
Low-Power Verification
Verification complexity and accuracy have become issues for power managed designs. Synopsys now delivers a complete and advanced low-power management verification solution in the industry.
Functional Equivalence Checking
Quickly verifying RTL-to-netlist functional equivalence for ultra-large ASIC, SoC and FPGA designs has traditionally been a challenge. Complex designs use numerous optimizations and are composed of extensive datapath, memory and full-custom blocks. Functional verification tools with easy-to-use, full-chip coverage are a requirement for market leading design flows.
Mixed-Signal Design and Verification
To meet the demands for more complex functionality and higher performance, today’s designs contain custom components that require schematic capture, simulation, and physical-layout design automation. Moreover, with < 90 nanometer geometries, and higher frequencies, digital logic circuits behave like analog circuits.
Synopsys’s analog and mixed-signal solutions address designers’ needs for comprehensive design and verification capabilities for custom digital, memory, mixed-signal and analog designs.
VCS Verification Library
The VCS Verification Library provides the industry’s broadest portfolio of verification IP for today’s most popular bus and I/O standards. It also includes Design Views for DesignWare Star IP processor cores and thousands of memory models. Written in OpenVera, the VCS Verification Library supports the Synopsys Reference Verification Methodology (RVM). The verification IP in the library integrates easily into OpenVera testbenches to generate bus traffic, insert error conditions, and check for protocol violations. The Monitors provide extensive reports to show functional coverage of the bus protocols
Languages
Today's system-on-a-chip designs require multi-discipline engineering teams with a range of skills covering embedded software, system architecture, RTL design and verification. Traditionally these teams use a variety of ‘C’ modeling styles for architecture design and a variety of hardware description languages (HDLs) and hardware verification languages (HVLs) for RTL design and verification. These traditional methods have led to very complex design flows, prohibited reuse, and have increased the total time to market and development costs for today’s chip designs.
Two industry standards have emerged to allow convergence of the different C-based and HDL and HVL-based approaches. These are SystemC, for C-based system-level modeling and SystemVerilog, providing a unified language for RTL design and verification. Both SystemC and SystemVerilog span multiple levels of abstraction.
- Standards-Related Links
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